1. Field of the Invention
Generally, the present disclosure relates to the field of the manufacture of integrated circuits and semiconductor devices, and, more particularly, to the detection of particle contamination of semiconductor wafers.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
The manufacturing of semiconductor devices requires high levels of cleanliness during the numerous manufacturing processes. For example, the surface of semiconductor wafers must be thoroughly cleaned of particle contaminants prior to processing. Further, films, such as dielectric films or metal films deposited on the semiconductor wafer, must also be thoroughly cleaned of particle contaminants. If not removed, contaminants on wafers and films may affect device performance characteristics and cause device failures to occur at faster rates than expected otherwise. Therefore, many of the processing steps are conducted in “clean rooms” to reduce possible particle contamination.
Nevertheless, semiconductor devices can become contaminated, and rendered defective, by contaminants during the various process steps. For example, during the various processing steps, contaminants may be introduced from the numerous processing tools because of incomplete cleansing of reagents from the tools.
Industry requirements for some processes, such as EUV lithography, require zero defects above 50 nm in size, since these are considered killer defects, and only a few defects can be tolerated between 20 nm and 50 nm. The defect requirements for other applications are less stringent, though the trends are driving towards less than 10 particles at continuously smaller sizes. The reduction of particles at such small sizes is producing extreme challenges for original equipment manufacturers (OEMs) as they must tightly control the performance of every component within the equipment, in addition to reducing process defects. The component suppliers face additional challenges as they not only have to meet the stringent performance specifications but also must improve performance based on continuously changing process latitudes and chemistries of end users.
One of the biggest challenges with such small defects is inspection and metrology. In the art, it is known to employ dark-field and bright-field microscopes or electron beam microscopes, possibly combined with a critical-dimension scanning or transmission microscope. However, sensibility for the detection of contaminating particles is not satisfying and state-of-the-art inspection tools can find defects only down to 30 nm on wafers and masks. Inspection tools capable of detecting smaller sizes are presently not available. Inspection and failure analysis tools that are capable of detecting defect sources below 50 nm are enormously costly, which causes a large infrastructure gap for suppliers working in component and material development. Lacking that infrastructure, it is very difficult for many OEMs and subsystem, component and material suppliers to reduce defect sources and improve defect performance.
Reducing particle contamination from semiconductor processing tools quickly is, therefore, of high importance. Tool downtime can be very costly as semiconductor processing is slowed or halted while the contamination source is located and cleaned. Further, accurately determining the source and eliminating the particle contamination is vital for producing high-quality semiconductor devices. Therefore, quickly and accurately determining the source of particle contamination in a semiconductor processing tool and returning the tool to service is of great importance.
In view of the situation described above, the present disclosure provides techniques for determining particle contamination of a semiconductor wafer in a reliable and fast, as well as non-destroying, manner, in particular, with high sensitivity and down to very small scales of below 30 nm.